Intricate signal processing of real world analog signals often requires signal conversion into the digital domain. Conversion makes feasible the use of either conventional digital computers or special purpose digital signal processors. Applications for such processing include wireless communications, such as portable voice, data, and messaging systems, that generally employ digital receivers to process transmitted complex high frequency RF signals. Such receivers typically acquire the RF analog signals in the gigahertz frequency range and translate the signals to lower intermediate frequencies, or IFs. Thereafter, the low IF signals are digitized and processed through digital signal processing components and techniques.
In order to initially sample such high frequency signals, however, the sampling rates applied to the analog RF signals are typically extremely high. This often requires the use of extremely high speed sample and hold circuits to conduct the sampling operation.
One technique for achieving high resolution of relatively low frequency signals with lower precision components utilizes oversampling or sigma-delta modulation followed by digital low pass filtering and decimation. Oversampling refers to operation of the modulator at a rate many times above the Nyquist rate, typically twice the bandwidth of the sampled analog signal. Decimation of the signals refers to reduction of the clock rate down to the Nyquist rate. Modulators of the sigma-delta type are often implemented in high resolution applications because of the ability to shape noise away from the sampled signals. Moreover, sigma-delta modulators offer the distinct advantage of multi-bit resolution with a single bit output.
The level of resolution in a sigma-delta modulator, or SDM, typically depends on the "order" of the device. The order is often determined by a somewhat complex transfer function that defines the circuit's frequency response characteristics. For example, a second order SDM typically has substantially better resolution and dynamic range than a first order SDM for the same oversampling ratio. While higher order SDM's are often more desirable to expand the dynamic range, or resolution of the device, a tradeoff usually exists in the form of increased hardware complexity.
Conventional sigma-delta modulation, while somewhat of a mature technology, has primarily focused on low pass architectures that rely on the assumption that the highest frequency component of the input analog signal corresponds to the signal bandwidth. Most low pass SDMs are based on a fundamental architecture comprising a subtractor that takes the difference between an analog signal input and a feedback signal to output a resultant error signal to the input of a feedforward loop filter. The filter generally comprises a discrete time integrator having a transfer function: ##EQU1## The output of the integrator feeds a quantizer which converts the filtered signal to a voltage corresponding to a mapped digital value. Generally, the quantizer has two output levels, one of which is sampled and fed back to the input subtractor as the feedback signal.
During operation, the circuit provides an oversampled sample stream output with low resolution, typically comprising one bit per sample. Additionally, quantization noise is shaped away from the signal into the higher frequency spectrum. The quantization noise is attenuated by the low pass decimation filter that follows the sigma delta modulator. The low pass decimation filter converts the low resolution oversampled sample stream into a high resolution Nyquist rate (or near Nyquist rate) sample stream. While the fundamental low pass sigma delta modulator architecture is beneficial for its intended purposes, the single integrator and quantizer design tends to be susceptible to instability at higher orders. Moreover, single components realizing higher-order functions tend to operate at slower speeds, substantially affecting the performance of the modulator.
One technique for allegedly improving the stability of low pass SDMs, and operating the components at a lower speed, involves implementing a time-interleaved parallel architecture. The time-interleaved circuit uses two identical, mutually cross-coupled modulators running at a sampling rate .function..sub.s to generate the same modulator transfer function, which runs at an equivalent sampling rate of 2.function..sub.s. The architecture includes a single sample and hold circuit operating at a sampling rate 2.function..sub.s. The sampled stream is split into the two branches, with each stream being down-sampled by two. The successive branches are time delayed at the respective inputs by a delay element. The down-sampled inputs feed respective modulator branches in substantially similar fashion to the fundamental low pass modulator described above. However, coupled between the respective branches are cross-coupled connections feeding the inputs of the other branch integrator inputs. The cross-coupled connection directed to the time delayed modulator includes a delay element to compensate for the delay caused at the subtractor input. Following quantization of the respective signals, the respective branch signals are upsampled by a factor of two and combined at a single adder to produce the resultant quantized signal at speed 2.function..sub.s.
While this circuit appears beneficial for its intended low pass purposes, it suffers from the drawback of requiring a relatively high speed sample and hold circuit operating at the overall circuit speed. Moreover, because of the asymmetrical structure of the branches caused by the additional delaying elements for the subsequently split branches, the overall circuit is susceptible to component mismatch effects.
Although low pass sigma delta modulation is an important sigma delta modulation technique, it fails to take advantage of bandpass signal conversion methods. To realize the benefits of bandpass conversion, the fundamental architecture for a bandpass SDM includes an adder having respective inputs for receiving a bandpass analog signal and a quantized feedback signal to produce an error signal output. The output of the adder feeds a feedforward loop filter having a bandpass transfer function characterized by: ##EQU2## A single quantizer or comparator disposed at the output of the filter converts the filtered signal to an analog voltage corresponding to a digital value. A feedback branch samples the output of the quantizer and directs the sampled output to the adder for summing with the analog input signal.
While this circuit works well for its intended purposes, the single filter and quantizer design tends to be susceptible to instability at higher orders, much like the fundamental low pass architecture. This is made more severe due to the high sampling rates required for the input sample and hold circuit. Moreover, single components realizing higher-order bandpass functions tend to operate at slower speeds, substantially affecting the performance of the modulator.
To minimize stability problems with individual higher-order components, an approach for implementing a bandpass SDM, disclosed in U.S. Pat. Nos. 5,341,136, 5,442,353, and 5,500,645, involves cascading low-order low pass SDMs to realize an overall higher-order bandpass modulator. This design has allegedly proven to reduce stability problems commonly associated with single component high order modulators, yet suffers from the drawback of an overall reduction in speed due to the cascaded configuration.
Therefore, the need exists for a parallel architecture for a bandpass sigma-delta modulator implementing low order components to effect a higher speed analog-to-digital converter. There also exists a need for such a modulator having the capability of operating at relatively high speeds and through a relatively high dynamic range. The sigma-delta modulator of the present invention satisfies these needs.